BEGIN:VCALENDAR VERSION:2.0 PRODID:-//linuxsoftware.nz//NONSGML Joyous v1.4//EN BEGIN:VEVENT SUMMARY:Nanoelectronic chip design: from physics principles to circuit des ign for production DTSTART:20251126T100000Z DTEND:20251126T120000Z DTSTAMP:20260812T210859Z UID:d2a0c031-0b13-46f4-98a7-200523267b1f SEQUENCE:2 CREATED:20251121T090558Z DESCRIPTION:LINKThis thesis presents the complete development workflow of a nanoelectronic device — from fabrication and electrical characterizati on to modeling and circuit-level design integration. The work focuses on t he memristor\, a passive two-terminal resistive device whose resistance de pends on the history of electrical stimuli\, thereby exhibiting memory. Su ch devices may play a key role in neuromorphic systems — computing archi tectures inspired by the human brain that promise large gains in energy ef ficiency and parallel information processing compared to conventional von Neumann systems. Two fabrication processes were developed to produce memri stors based on MgO and Si/Ag resistive switching mechanisms\, both yieldin g functional devices. The MgO devices exhibited OFF/ON ratios of approxima tely 10⁴ and switching voltages of 1.5 V (SET) and –0.2 V (RESET)\, wh ile the Si/Ag devices showed ratios up to 10⁶ with lower activation volt ages of 0.3 V (SET) and –0.1 V (RESET). A dedicated setup was developed to measure the noise spectral density of memristive devices and was used t o characterize commercial Knowm memristors\, revealing a correlation betwe en device resistance and noise amplitude. A voltage-controlled memristor m odel based on the VTEAM formulation was implemented in Verilog-A and valid ated through simulations in Cadence Virtuoso\, enabling its integration in to circuit-design workflows at INESC MN. Additionally\, a low-power\, low- noise neural preamplifier was designed\, achieving a gain of 66 dB and an input-referred noise of 17 µV\, suitable for integration in a memristor-b ased neuromorphic circuit. LAST-MODIFIED:20251121T090606Z LOCATION:Online URL:http://df.vps.tecnico.ulisboa.pt/pt/eventos/nanoelectronic-chip-design -from-physics-principles-to-circuit-design-for-production/ X-ALT-DESC;FMTTYPE=text/html:

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This thesis presents th e complete development workflow of a nanoelectronic device — from fabric ation and electrical characterization to modeling and circuit-level design integration. The work focuses on the memristor\, a passive two-terminal r esistive device whose resistance depends on the history of electrical stim uli\, thereby exhibiting memory. Such devices may play a key role in neuro morphic systems — computing architectures inspired by the human brain th at promise large gains in energy efficiency and parallel information proce ssing compared to conventional von Neumann systems.

Two fabricat ion processes were developed to produce memristors based on MgO and Si/Ag resistive switching mechanisms\, both yielding functional devices. The MgO devices exhibited OFF/ON ratios of approximately 10⁴ and switching volt ages of 1.5 V (SET) and –0.2 V (RESET)\, while the Si/Ag devices showed ratios up to 10⁶ with lower activation voltages of 0.3 V (SET) and –0. 1 V (RESET). A dedicated setup was developed to measure the noise spectral density of memristive devices and was used to characterize commercial Kno wm memristors\, revealing a correlation between device resistance and nois e amplitude. A voltage-controlled memristor model based on the VTEAM formu lation was implemented in Verilog-A and validated through simulations in C adence Virtuoso\, enabling its integration into circuit-design workflows a t INESC MN. Additionally\, a low-power\, low-noise neural preamplifier was designed\, achieving a gain of 66 dB and an input-referred noise of 17 µ V\, suitable for integration in a memristor-based neuromorphic circuit.

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