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SUMMARY:Plasmas for Microelectronics Fabrication: A Modeling Perspective
DTSTART:20230329T160000Z
DTEND:20230329T170000Z
DTSTAMP:20260623T162247Z
UID:e86a9ffd-6820-4488-ad68-a0ebb1dcebd9
SEQUENCE:4
CREATED:20230130T132544Z
DESCRIPTION:Speaker: Prof. Mark Kushner\, The University of MichiganTitle:
  Plasmas for Microelectronics Fabrication: A Modeling PerspectiveAbstract:
  The impressive advances in the capabilities of microelectronics logic and
  memory devices are largely due to plasma-based etching\, deposition\, cle
 aning\, sputtering and passivation processes that have been translated to 
 high volume manufacturing (HVM). Memory device architectures require etchi
 ng high aspect ratio (HAR) features of only tens of nm diameter with aspec
 t ratios exceeding 100. Logic devices now require removing or adding mater
 ials with atomic layer accuracy – atom layer etching (ALE) and atomic la
 yer deposition (ALD). These manufacturing steps can now only be provided i
 n HVM using plasma processes. Modeling and simulation (M&amp\;S) for both 
 reactor and feature scale plasma processing has long served a supporting r
 ole. However\, with HAR\, ALE and HVM challenges at the forefront\, M&amp\
 ;S for plasma based device fabrication has received renewed attention to p
 rovide (or inspire) new equipment and process designs\, and new insights. 
 In this talk\, the status of M&amp\;S for plasma processing will be survey
 ed. An overview and &quot\;quick-plasma&quot\; tutorial will first be prov
 ided\, followed by a description of the numerical techniques used for reac
 tor and feature scale modeling. Using examples from the speaker’s resear
 ch group\, the model-based scaling and optimization of plasma etching reac
 tors will be discussed (e.g.\, multi-frequency\, capacitively coupled plas
 mas for HAR etching and pulsed inductively coupled plasmas for front-end p
 rocessing). The coupling of reactor-scale reactive fluxes to feature scale
  modeling of ALE and ALD\, and HAR of ONO (oxide-nitride-oxide) stacks for
  high-density memory will be discussed\, as well the role of machine learn
 ing for process design.*Work supported by the DOE Office of Fusion Energy 
 Science\, National Science Foundation\, Lam Research Inc. and Samsung Elec
 tronics Co. Ltd.
LAST-MODIFIED:20230130T195614Z
LOCATION:PA1\, Mathematics
URL:http://df.vps.tecnico.ulisboa.pt/pt/eventos/plasmas-for-microelectroni
 cs-fabrication-a-modeling-perspective/
X-ALT-DESC;FMTTYPE=text/html:<p data-block-key="q6fob">Speaker: Prof. Mark
  Kushner\, The University of Michigan</p><p data-block-key="c84ju">Title: 
 Plasmas for Microelectronics Fabrication: A Modeling Perspective</p><p dat
 a-block-key="c7i6v"></p><p data-block-key="26l0l">Abstract: The impressive
  advances in the capabilities of microelectronics logic and memory devices
  are largely due to plasma-based etching\, deposition\, cleaning\, sputter
 ing and passivation processes that have been translated to high volume man
 ufacturing (HVM). Memory device architectures require etching high aspect 
 ratio (HAR) features of only tens of nm diameter with aspect ratios exceed
 ing 100. Logic devices now require removing or adding materials with atomi
 c layer accuracy – atom layer etching (ALE) and atomic layer deposition 
 (ALD). These manufacturing steps can now only be provided in HVM using pla
 sma processes. Modeling and simulation (M&amp\;S) for both reactor and fea
 ture scale plasma processing has long served a supporting role. However\, 
 with HAR\, ALE and HVM challenges at the forefront\, M&amp\;S for plasma b
 ased device fabrication has received renewed attention to provide (or insp
 ire) new equipment and process designs\, and new insights. In this talk\, 
 the status of M&amp\;S for plasma processing will be surveyed. An overview
  and &quot\;quick-plasma&quot\; tutorial will first be provided\, followed
  by a description of the numerical techniques used for reactor and feature
  scale modeling. Using examples from the speaker’s research group\, the 
 model-based scaling and optimization of plasma etching reactors will be di
 scussed (e.g.\, multi-frequency\, capacitively coupled plasmas for HAR etc
 hing and pulsed inductively coupled plasmas for front-end processing). The
  coupling of reactor-scale reactive fluxes to feature scale modeling of AL
 E and ALD\, and HAR of ONO (oxide-nitride-oxide) stacks for high-density m
 emory will be discussed\, as well the role of machine learning for process
  design.</p><p data-block-key="3b4rn"></p><p data-block-key="3k9vq">*Work 
 supported by the DOE Office of Fusion Energy Science\, National Science Fo
 undation\, Lam Research Inc. and Samsung Electronics Co. Ltd.</p>
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