Nanoelectronic chip design: from physics principles to circuit design for production

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This thesis presents the complete development workflow of a nanoelectronic device — from fabrication and electrical characterization to modeling and circuit-level design integration. The work focuses on the memristor, a passive two-terminal resistive device whose resistance depends on the history of electrical stimuli, thereby exhibiting memory. Such devices may play a key role in neuromorphic systems — computing architectures inspired by the human brain that promise large gains in energy efficiency and parallel information processing compared to conventional von Neumann systems.

Two fabrication processes were developed to produce memristors based on MgO and Si/Ag resistive switching mechanisms, both yielding functional devices. The MgO devices exhibited OFF/ON ratios of approximately 10⁴ and switching voltages of 1.5 V (SET) and –0.2 V (RESET), while the Si/Ag devices showed ratios up to 10⁶ with lower activation voltages of 0.3 V (SET) and –0.1 V (RESET). A dedicated setup was developed to measure the noise spectral density of memristive devices and was used to characterize commercial Knowm memristors, revealing a correlation between device resistance and noise amplitude. A voltage-controlled memristor model based on the VTEAM formulation was implemented in Verilog-A and validated through simulations in Cadence Virtuoso, enabling its integration into circuit-design workflows at INESC MN. Additionally, a low-power, low-noise neural preamplifier was designed, achieving a gain of 66 dB and an input-referred noise of 17 µV, suitable for integration in a memristor-based neuromorphic circuit.