Plasmas for Microelectronics Fabrication: A Modeling Perspective

Speaker: Prof. Mark Kushner, The University of Michigan

Title: Plasmas for Microelectronics Fabrication: A Modeling Perspective

Abstract: The impressive advances in the capabilities of microelectronics logic and memory devices are largely due to plasma-based etching, deposition, cleaning, sputtering and passivation processes that have been translated to high volume manufacturing (HVM). Memory device architectures require etching high aspect ratio (HAR) features of only tens of nm diameter with aspect ratios exceeding 100. Logic devices now require removing or adding materials with atomic layer accuracy – atom layer etching (ALE) and atomic layer deposition (ALD). These manufacturing steps can now only be provided in HVM using plasma processes. Modeling and simulation (M&S) for both reactor and feature scale plasma processing has long served a supporting role. However, with HAR, ALE and HVM challenges at the forefront, M&S for plasma based device fabrication has received renewed attention to provide (or inspire) new equipment and process designs, and new insights. In this talk, the status of M&S for plasma processing will be surveyed. An overview and "quick-plasma" tutorial will first be provided, followed by a description of the numerical techniques used for reactor and feature scale modeling. Using examples from the speaker’s research group, the model-based scaling and optimization of plasma etching reactors will be discussed (e.g., multi-frequency, capacitively coupled plasmas for HAR etching and pulsed inductively coupled plasmas for front-end processing). The coupling of reactor-scale reactive fluxes to feature scale modeling of ALE and ALD, and HAR of ONO (oxide-nitride-oxide) stacks for high-density memory will be discussed, as well the role of machine learning for process design.

*Work supported by the DOE Office of Fusion Energy Science, National Science Foundation, Lam Research Inc. and Samsung Electronics Co. Ltd.